The technology disclosed herein relates to configurations of semiconductor devices including a semiconductor element and a mounting substrate, and more particularly, to configurations and methods for connecting a semiconductor element with a mounting substrate.
In recent years, in order to simultaneously increase the density of circuitry provided in a semiconductor element and the number of pins of electrode terminals, attempts have been made to reduce the pitch and area of the electrode terminals of the semiconductor element. To achieve this, when the semiconductor element is mounted onto a mounting substrate by a flip chip mounting technique, a strict requirement is placed on a sealing resin which is injected between the semiconductor element and the mounting substrate.
In typical flip chip mounting, protruding electrodes such as solder bumps or the like are formed on electrode terminals of a semiconductor element such as an LSI or the like, and the resultant semiconductor element is bump-connected and mounted to connection terminals of a mounting substrate by pressure bonding and heating.
However, the pitch has been significantly narrowed, and therefore, if electrode terminals are provided at a periphery of the semiconductor substrate as in the conventional art, a short circuit may occur between the electrode terminals, and a connection fault or the like may occur due to a distortion caused by a difference in thermal expansion coefficient between the semiconductor element and the mounting substrate. Therefore, the pitch of electrode terminals has been broadened by arranging the electrode terminals two-dimensionally. However, the pitch has recently been significantly narrowed even in two-dimensional arrangements.
Flip chip bonding using solder bumps may be carried out by the following known method: washing is performed using flux after solder bonding, and a sealing resin is injected before being thermally cured. In this method, after the flux is supplied onto electrodes of a mounting substrate, a semiconductor element on which solder bumps have been formed are positioned and mounted onto the mounting substrate. Thereafter, the solder is melted and bonded by heating means such as a reflow furnace or the like before the flux component is dissolved and washed out by immersing the mounting substrate in washing liquid. Thereafter, a sealing resin is injected, using a dispenser or the like, into a void between the semiconductor element and the mounting substrate so as to enhance the reliability of resistance to falling and bending of the solder bonding portions, and thereafter, the sealing resin is thermally cured. However, in recent years, the pitch of the solder bonding portions has been narrowed and the gap between the semiconductor element and the electrode of the mounting substrate has also been reduced, and therefore, it is difficult for washing liquid to circulate, so that flux residues remain on the mounting substrate. As a result, the following drawbacks may occur: an open circuit fault or peeling-off occurring in use environments; and the void is too narrow to exhibit the effect of capillarity, and therefore, it takes time to inject the sealing resin and the aforementioned bonding method is not applicable to manufacture.
In order to reduce or avoid such drawbacks, a sealing adhesive containing flux may be supplied onto a substrate, and thereafter, a semiconductor element on which solder bumps have been formed may be mounted onto the substrate, and the sealing adhesive may be thermally cured by heating and pressing means, simultaneously with solder bonding (see, for example, Japanese Patent No. 2589239). FIGS. 12A and 12B are cross-sectional views showing a conventional semiconductor element mounting method described in Japanese Patent No. 2589239. In this method, an adhesive material 120 containing flux is supplied onto a substrate 100, and thereafter, solder bumps 140 provided on an active surface (circuit-formed surface) of a semiconductor element 130 are connected with a metallized pattern 110 provided on the substrate 100.
However, when this method is applied to a thin semiconductor element, the pressure may cause the sealing adhesive to overflow and extend around to a back surface of the semiconductor element. In this case, the semiconductor element may be broken due to a difference in linear expansion coefficient between the semiconductor substrate and the sealing adhesive when heat is applied thereto during reflowing or the like after thermal curing.
Therefore, a sealing film containing flux may be provided on the substrate so that the amount of the sealing adhesive can be easily controlled, thereby reducing the sealing adhesive flowing around to the back surface of the semiconductor element (see, for example, Japanese Patent No. 4047754). Another technique has been described in Japanese Patent Laid-Open Publication No. 2005-223330.